快樂(lè)蝦

http://blog.csdn.net/lights_joy/

lights@hb165.com

本文適用于

ADI bf561 DSP

uclinux-2008r1.5-rc3 ( 移植到 vdsp5)

Visual DSP++ 5.0(update 5)

歡迎轉(zhuǎn)載，但請(qǐng)保留作者信息

/* Initialise UART - when booting from u-boot, the UART is not disabled

* so if we dont initalize here, our serial console gets hosed */

p0.h = hi(UART_LCR);

p0.l = lo(UART_LCR);

r0 = 0x0(Z);

w[p0] = r0.L; /* To enable DLL writes */

ssync;

p0.h = hi(UART_DLL);

p0.l = lo(UART_DLL);

r0 = 0x0(Z);

w[p0] = r0.L;

ssync;

p0.h = hi(UART_DLH);

p0.l = lo(UART_DLH);

r0 = 0x00(Z);

w[p0] = r0.L;

ssync;

p0.h = hi(UART_GCTL);

p0.l = lo(UART_GCTL);

r0 = 0x0(Z);

w[p0] = r0.L; /* To enable UART clock */

ssync;

這段代碼用于關(guān)閉串串口，但是這里有個(gè)問(wèn)題，在設(shè)置 UART_DLL 和 UART_DLH 時(shí)必須將 UART_LCR 的最高位設(shè)置為 1 ，但是原始代碼中卻未設(shè)置，這樣就造成了設(shè)置 UART_DLL 和 UART_DLH 必然失敗。所以

r0 = 0x0(Z);

應(yīng)該改為

r0 = 0x80(Z);

下面的說(shuō)明來(lái)自于 vdsp 文檔：

The UART _ DLL register is mapped to the same address as the UART_THR and UART_RBR registers. The UART_DLH register is mapped to the same address as the Interrupt Enable register ( UART_IER ). The DLAB bit in UART_LCR must be set before the UART Divisor Latch registers can be accessed.

在將 UART_DLH 和 UART_DLL 置 0 后，它的 Divisor 將變成 65536 。

這一句

w[p0] = r0.L; /* To enable UART clock */

也相當(dāng)奇怪，如果按照注釋的說(shuō)法是要啟用 UART clock ，但是將 UART_GCTL 的值設(shè)置為 0 卻明顯是關(guān)閉 clock 。

1 參考資料

head.s 分析 (1) ：保存 u-boot 傳遞過(guò)來(lái)的指針 (2009-1-19)

head.s 分析 (2) ： SYSCFG 配置 (2009-1-19)

head.s 分析 (3) ：數(shù)據(jù)及指針寄存器清 0 (2009-1-19)

head.s 分析 (4) ：關(guān)閉 CACHE (2009-01-19)

head.s分析(5)：關(guān)閉串口